A Three-Dimensional Integration Technology with Embedded Au Electrodes for Stacked CMOS Image Sensors

We report on a novel 3D integration technology suitable for stacked CMOS image sensors by using high-density Au electrodes embedded within every pixel for vertical interconnection between silicon-on-insulator (SOI) layers. Unlike the conventional technique based on the through silicon vias (TSVs) or microbumps, the presented process is suitable for ultra-high-density 3D integration within an imaging pixel area of a few micrometers or less. We demonstrate a successful operation of the developed stacked CMOS image sensors and also evaluate the performance of the developed process, which indicates the technology is promising for high-density stacked CMOS image sensor. Introduction Vertical stacking of signal processing circuits is a More-than-Moore type solution to deliver multifunctions to CMOS image sensors such as high resolution, high sensitivity, and fast signal processing speed. Recent demands for higher density of sensors such as 8K imagers are escalating to reduce their pixel area down to a few μm. Previous works report on stacked image sensors [1-4] by using the TSV and microbump technologies. However, the diameter of the TSVs or bumps was usually larger than the imaging pixel, and such electrical interconnection is shared by multiple pixels, thereby limiting the throughput of signal processing speed. Fabrication technology To overcome this problem, we have developed a 3D integration technology without TSVs or bumps, as illustrated in Fig. 1 in comparison with conventional 2D sensor. Several functional layers such as photodiode (PD) and signal processors are vertically stacked, where Au interconnect electrodes are embedded in every pixel. Fig. 2 shows the fabrication process: (a) FETs for signal processor and PD are formed on a fully-depleted (FD) SOI wafer. (b) After an intermediate layer of SiO2 is patterned, a Au layer is electroplated. (c) Chemical mechanical polishing (CMP) is applied to form embedded Au electrodes. (d) After dicing into 20-mmsquare chips, the surface is activated by Ar and O2 plasma and then directly bonded at 200 degree C. (e) To allow incident light come into the PD, the handle layer of the PD chip is grinded first and then finally removed by XeF2 vapor phase etching. The direct bonding process allows the embedded Au electrodes smaller than 1 μm in diameter. This process can be extended to more than three-layers of stacking by repeating the above processes.